DDR can manipulate data two times per clock cycle. This means the output is twice that of the front side BUS (FSB).
DDR | Output | FSB | Peak Bandwidth |
PC1600 | 200Mhz | 100Mhz | 1.6GB/sec |
PC2100 | 266Mhz | 133Mhz | 2.1GB/sec |
PC2700 | 333Mhz | 166Mhz | 2.7GB/sec |
PC3200 | 400Mhz | 200Mhz | 3.2GB/sec |
DDR2 | Output | FSB | Peak Bandwidth |
PC2-3200 | 400Mhz | 200Mhz | 3.2GB/sec |
PC2-4200 | 533Mhz | 266Mhz | 4.2GB/sec |
PC2-5300 | 667Mhz | 333Mhz | 5.3GB/sec |
PC2-6400 | 800Mhz | 400Mhz | 6.4GB/sec |
DDR2 3 | Output | FSB | Peak Bandwidth |
PC3-6400 | 800Mhz | 400Mhz | 6.4GB/sec |
PC3-8500 | 1066Mhz | 533Mhz | 8.5GB/sec |
PC3-5300 | 1333Mhz | 666Mhz |
10.6GB/sec |